DS1629S+T&R【PDF 11/23 页】IC THERM/RTC/CALENDAR DIG 8-SOIC

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DS1629

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CAL = Clock Alarm Latch. This volatile status bit will be set to 1 when the clock comparator becomes

active. Once set, it will remain latched until DS1629 power is cycled. A 0 in this location indicates the

clock has never been in an alarm condition since the DS1629 was powered-up. This is a read-only bit

(writes to this location constitute a dont care) and the power-up default is the flag cleared (CAL = 0).

TAL = Thermal Alarm Latch. This volatile status bit will be set to 1 when the thermal comparator

becomes active. Once set, it will remain latched until DS1629 power is cycled. A 0 in this location

indicates the DS1629 temperature has never exceeded T

since power-up. This is a read-only bit (writes

to this location constitute a dont care) and the power-up default is the flag cleared (TAL = 0).

0 = Dont care. Dont care on a write, but will always read out as a 0.

2-WIRE SERIAL DATA BUS

The DS1629 supports a bidirectional two-wire bus and data transmission protocol. A device that sends

data onto the bus is defined as a transmitter, and a device receiving data as a receiver. The device that

controls the message is called a master. The devices that are controlled by the master are slaves. The

bus must be controlled by a master device which generates the serial clock (SCL), controls the bus access,

and generates the START and STOP conditions. The DS1629 operates as a slave on the 2-wire bus.

Connections to the bus are made via the open-drain I/O lines SDA and SCL.

The following bus protocol has been defined:

" Data transfer may be initiated only when the bus is not busy.

" During data transfer, the data line must remain stable whenever the clock line is high. Changes in the

data line while the clock line is high will be interpreted as control signals.

Accordingly, the following bus conditions have been defined:

Bus not busy: Both data and clock lines remain high.

Start data transfer: A change in the state of the data line, from high to low, while the clock is high,

defines a START condition.

Stop data transfer: A change in the state of the data line, from low to high, while the clock line is HIGH,

defines the STOP condition.

Data valid: The state of the data line represents valid data when, after a START condition, the data line

is stable for the duration of the high period of the clock signal. The data on the line must be changed

during the low period of the clock signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a START condition and terminated with a STOP condition. The

number of data bytes transferred between START and STOP conditions is not limited, and is determined

by the master device. The information is transferred byte-wise and each receiver acknowledges with a 9th

bit.

The maximum clock rate of the DS1629 is 400kHz.

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